A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators

A wide bandwidth, high sample rate 3 order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuitand architecture-level techniques. Fabricated in 65nm CMOS, the prototype modulator operates at 1.28GS/s and achieves a dynamic range of 75dB, SNR of 71dB in 50MHz bandwidth, while consuming 38mW of total power. Introduction Voltage-controlled-oscillator (VCO) based ADCs exhibit many desirable properties such as inherent quantization noise shaping, implicit anti-aliasing, and guaranteed monotonicity. Because they can be implemented using mostly digital circuits, their performance (resolution and energy efficiency) improves with technology scaling. A majority of the VCO-based ADCs are implemented using the feed-forward (FF) topology in which the VCO converts input voltage (VIN) to frequency and a frequency-to-digital quantizer generates the noise-shaped digital output [1-5]. They suffer from two main drawbacks. First, because VIN spans the entire tuning range of the VCO, such ADCs are susceptible to the non-linear voltage-to-frequency (V-to-F) transfer characteristic. Second, the order of noise shaping is limited to the first order, which makes it difficult to increase the signal bandwidth without compromising dynamic range. Calibration can help alleviate the impact of nonlinearity [1-2], but increasing the order mandates that VCO-based ADC be placed in the backend of a